Technologies using a direct conversion system have been proposed with recent progress in reducing the size and cost of a radio receiver. This system directly converts an RF input signal into a low-frequency baseband signal, and therefore is advantageous, e.g., in eliminating an intermediate frequency filter as compared to a conventional system that requires the intermediate frequency.
A frequency conversion is performed by mixing an RF input signal and a local signal whose frequency is equal to that of the RF input signal. In the direct conversion system, however, if there is second order nonlinear distortion in a mixer, and the input signal level is high, a DC offset occurs in the output baseband signal. This case will be described in detail by referring to FIGS. 10 and 11. FIG. 10 shows the spectrum of the RF input signal. Reference numeral 61 denotes a weak-level desired signal that has a center frequency equal to a local signal frequency fLO. Reference numeral 62 denotes a high-level interfering signal that has a frequency fINT higher than the local signal frequency fLO.
When the RF input signal including such a high-level interfering signal is input to the mixer, the output signal of the mixer has a spectrum as shown in FIG. 11. Reference numerals 63, 64 denote components of the mixer output after the frequency conversion of the desired signal 61 and the interfering signal 62 of the RF input signal, respectively. Reference numeral 65 denotes a DC offset caused by the high-level interfering signal in the presence of second order nonlinear distortion of the mixer.
In the direct conversion system, the DC offset 65 occurs within the band of the desired signal 63 of the mixer output, and thus reduces the reception sensitivity. If the mixer is composed of a differential circuit, and the differential balance is perfectly symmetrical, the second order nonlinear distortion is not present. Actually, however, the elements constituting the differential circuit cannot have perfect symmetry due to manufacturing variations. Therefore, it is not possible to eliminate the second order nonlinear distortion.
On the other hand, in the direct conversion system, leakage of the local signal frequency fLO into the RF input terminal may result in self-mixing of the mixer. The self-mixing also causes a DC offset in the mixer output, even if the input signal level is low. This case will be described in detail by referring to FIGS. 12 and 13. FIG. 12 shows the spectrum of the RF input signal. Reference numeral 66 denotes a spectrum that indicates the leakage of the local signal frequency fLO into the RF input terminal. When the local signal 66 that has leaked into the RF input terminal is input to the mixer, the output signal of the mixer has a spectrum as shown in FIG. 13. Reference numerals 67, 68 denote spectrums obtained by the frequency conversion using the local signal frequency fLO: 67 is a DC offset, and 68 is a signal having a frequency of 2×fLO.
In the direct conversion system, the DC offset 67 occurs due to self-mixing within the band of the desired signal of the mixer output, and thus reduces the reception sensitivity. Because of the asymmetry of a layout of the mixer or the parasitic components of devices constituting the mixer, the self-mixing cannot be removed completely. Therefore, it is not possible to make the DC offset zero in the mixer output.
The low-frequency baseband signal output from the mixer enters a baseband block. The baseband block includes a filter that attenuates the interfering wave other than the desired signal at the RF input terminal, and an amplifier that can vary the gain for maintaining the amplitude of the baseband signal constant at the output terminal of the baseband block, regardless of the magnitude of the input signal from the RF input terminal. However, neither the filter nor the differential circuit of the amplifier can have perfect symmetry due to manufacturing variations. Therefore, a DC offset also occurs in the baseband block. Consequently, the DC offset that has occurred in the mixer output by self-mixing and has been multiplied by the gain of the amplifier is combined with the DC offset that has occurred in the baseband block, and then is output from the output terminal of the baseband block.
As described above, two types of DC offsets are problems for a direct conversion receiver and are categorized as: a DC offset that varies depending on the RF input signal; and a DC offset that is kept constant regardless of the RF input signal. The former can be referred to as “dynamic DC offset”, and the latter can be referred to as “static DC offset”.
Conventionally, techniques of compensating both for the dynamic DC offset and the static DC offset have been proposed.
U.S. Pat. No. 6,535,725 discloses a method for compensating for a dynamic DC offset that occurs in the output of a mixer by detecting an interfering signal included in an RF input signal. First, this method will be described by referring to FIG. 14.
In FIG. 14, a mixer 73 includes a switching cell 71 and an RF input cell 72. In the RF input cell 72, an RF input signal is input from RF input terminals 83, 84 and amplified. In the switching cell 71, the amplified RF signal is mixed with a local signal that is input from local input terminals 81, 82, and thus is converted into an IF signal. The IF signal is output from output terminals 79, 80. The direct conversion system also is called “zero IF system”, since the center frequency of the IF signal is at DC.
The switching cell 71 includes bipolar transistors Q1, Q2, Q3, and Q4. If all the transistors have exactly the same properties, the balance of a differential circuit is perfectly symmetrical. However, the properties of the individual transistors Q1, Q2, Q3 and Q4 deviate from the ideal properties due to manufacturing variations. Therefore, second order nonlinear distortion may occur during the conversion of the RF input signal into the IF signal. This leads to a DC offset in the mixer output, as shown in FIG. 11. As is well known, the DC offset is proportional to the square of the input signal strength. Accordingly, the DC offset of the mixer output is increased as the level of the interfering wave included in the input signal becomes higher.
A DC offset compensator 78 includes a detector 76, a controller 75, a correction generator 74, and a user interface 77. The detector 76 detects the RF input signal and outputs a detection signal. The controller 75 generates a control signal in accordance with the detection signal. The correction generator 74 generates a correction signal in accordance with the control signal of the controller 75 so as to reduce the DC offset at the output terminals 79, 80 of the mixer 73. The operation of the DC offset compensator 78 allows the correction signal of the correction generator 74 to change with the strength of the RF signal input to the mixer 73, thereby compensating for the DC offset of the mixer output. The second order nonlinear distortion of the mixer 73 is caused by manufacturing variations and differs in characteristics individually. Thus, the DC offset compensator 78 further has the function of adjusting the control signal of the controller 75 with the user interface 77.
Next, a method for compensating for the static DC offset that occurs at the output terminal of a baseband block will be described by referring to FIG. 15. FIG. 15 shows the basic configuration of a conventional DC offset calibration system.
In FIG. 15, reference numeral 1 denotes an RF amplifier composed of a LNA (low noise amplifier) for amplifying a high-frequency signal, 2 denotes a mixer for converting an RF input signal into a low-frequency baseband signal, and 3 denotes a local signal generator. A local signal that has leaked into RF input terminals 16, 17 is amplified by the RF amplifier 1, combined with a local signal that has leaked into mixer input terminals 20, 21, and appears at the mixer input terminals 20, 21 as represented by 66 in FIG. 12. This local signal appearing at the mixer input terminals 20, 21 is mixed with a local signal that has a frequency of fLO and is generated from output terminals 22, 23 of the local signal generator 3, so that the frequency is converted, and the DC offset 67 as shown in FIG. 13 occurs at output terminals 24, 25 of the mixer 2.
In FIG. 15, reference numeral 4 denotes a baseband block that includes a LPF (low-pass filter) 5 for attenuating an interfering signal and an AMP 6. The AMP 6 has a variable gain function for maintaining the magnitude of the baseband signal constant, regardless of the magnitude of the RF input signal from the RF input terminals 16, 17. The DC offset 67 and the 2×fLO component 68 caused by self-mixing (FIG. 13) are output from the output terminals 24, 25 of the mixer 2 and input to the LPF 5. Then, the 2×fLO component 68 is attenuated fully. The DC offset 67 appears at output terminals 26, 27 of the LPF 5, is amplified by the AMP 6, and appears at baseband output terminals 28, 29. Because of the asymmetry of a differential circuit of the baseband block 4, a DC offset also occurs in the baseband block 4. Consequently, the DC offset caused by self-mixing and the DC offset that occurred in the baseband block 4 are combined and output from the baseband output terminals 28, 29.
In FIG. 15, a static DC offset compensator 7 includes a comparator 8, a successive approximation register (referred to as “SAR” in the following) 9, and a D/A converter (referred to as “DAC” in the following) 10a. The comparator 8 is used to discriminate the polarity of the DC offset at the baseband output terminals 28, 29. The SAR 9 compares the output signal of the comparator 8 with the polarity of the initial discrimination and outputs zero if the polarity is changed, and outputs 1 if the polarity is unchanged. The DAC 10a converts the digital signal output from the SAR 9 into an analog signal.
The comparator 8 and the SAR 9 constitute a successive approximation A/D converter. The DC offset that occurs in the baseband output is an analog signal, and therefore is converted into a digital signal by the successive approximation A/D converter. The converted digital signal is returned to an analog signal by the DAC 10a. The signal of the baseband output terminals 28, 29 is supplied to the input of the static DC offset compensator 7, and the output of the static DC offset compensator 7 is supplied to the output terminals 24, 25 of the mixer 2, thus forming a feedback loop. The static DC offset compensator 7 supplies a compensation current to the output terminals 24, 25 of the mixer 2 so as to compensate for the DC offset appearing at the baseband output terminals 28, 29.
Referring to FIGS. 16 to 20, the operation of the static DC offset compensator 7 and the process of compensating for the static DC offset will be described in detail, while taking the DAC 10a with 5 bits as an example.
FIG. 16 is a flowchart for explaining the operation of the static DC offset compensator 7.
FIG. 17 shows the relationship between a compensation current flowing into the output terminals 24, 25 (FIG. 15) of the mixer and the amount of a DC offset that occurs for the compensation current. The horizontal axis indicates the magnitude of the compensation current, and the vertical axis indicates the amount of the DC offset appearing at the baseband output terminals 28, 29. In FIG. 17, a line 71 represents the relationship between the amounts of the compensation current and the DC offset when an initial DC offset is output in the positive direction, and a line 72 represents the relationship between the amounts of the compensation current and the DC offset when an initial DC offset is output in the negative direction. The static DC offset compensator 7 switches the polarity of the compensation current in accordance with the polarity of the initial DC offset. For both the lines 71 and 72, the DC offset at the baseband output terminals 28, 29 becomes smaller as the absolute value of the compensation current is increased from the origin on the horizontal axis. Thus, the static DC offset has the characteristics that the amount of the DC offset that occurs in the baseband output is reduced with an increase in the absolute value of the compensation current. Therefore, the DC offset at the baseband output terminals 28, 29 can be adjusted by adjusting the absolute value of the compensation current in accordance with the polarity of the DC offset occurred.
FIGS. 18 and 19 show the process of adjusting the DC offset and correspond to FIG. 17. The vertical axis indicates the amount of the DC offset appearing at the baseband output terminals 28, 29, and the horizontal axis indicates time. FIG. 20 is a read table for each bit of the DAC 10a. The output of the DAC 10a is set so that the compensation current is increased monotonically from LSB to MSB.
The process of adjusting the DC offset when the initial DC offset is output in the positive direction as represented by the line 71 in FIG. 17 will be described below.
In FIG. 16, the static DC offset compensator 7 starts operating in the step S1. In the step S2, all the bits of the DAC 10a are set to zero, so that the read value of the DAC 10a is 00000, and no compensation current is output from the DAC 10a. Therefore, a DC offset in the initial state that corresponds to a time t10 of the line 71 in FIG. 17 occurs at the baseband output terminals 28, 29. The adjustment is performed to reduce this value. Subsequently, in the step S3, the comparator 8 detects the initial DC offset. In the step S4, MSB of the DAC 10a is set to 1 by the SAR 9, and the DAC 10a outputs a compensation current in accordance with 10000. Thus, a DC offset corresponding to a time till of the line 71 in FIG. 17 occurs.
Next, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t10 with the DC offset at the time t11 of the line 71 in FIG. 17. Both the output values at t10 and t11 are positive, and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 11000. The DAC 10a outputs a compensation current in accordance with 11000, and a DC offset corresponding to a time t12 of the line 71 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t10 with the DC offset at the time t12. As shown in FIG. 17, both the output values at t10 and t12 are positive and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 11100. The DAC 10a outputs a compensation current in accordance with 11100, and a DC offset corresponding to a time t13 of the line 71 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t10 with the DC offset at the time t13. As shown in FIG. 17, the output values at t10 and t13 are inverted. Therefore, in the step S7, the present bit is returned to zero, and 11000 is read from the SAR 9. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 11010. The DAC 10a outputs a compensation current in accordance with 11010, and a DC offset corresponding to a time t14 of the line 71 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t10 with the DC offset at the time t14. As shown in FIG. 17, the output values at t10 and t14 are inverted. Therefore, in the step S7, the present bit is returned to zero, and 11000 is read from the SAR 9. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 11001. The DAC 10a outputs a compensation current in accordance with 11001, and a DC offset corresponding to a time t15 of the line 71 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t10 with the DC offset at the time t15. As shown in FIG. 17, both the output values at t10 and t15 are positive and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is YES, 11001 is stored in the DAC 10a. In the step S10, the operation is END, and the DC offset compensation is finished.
The above operation can be summarized in FIG. 18. The initial DC offset at t10 is approximated successively during the time from t11 to t15 and compensated in the direction of decreasing the DC offset. At t16, the DC offset compensation is finished with the storage of 11001 in the DAC 10a, and the static DC offset that is output in the positive direction at the baseband output terminals 28, 29 can be compensated.
Next, the process of adjusting the DC offset when the initial DC offset is output in the negative direction as represented by the line 72 in FIG. 17 will be described below.
In FIG. 16, the static DC offset compensator 7 starts operating in the step S1. In the step S2, all the bits of the DAC 10a are set to zero, so that the read value of the DAC 10a is 00000, and no compensation current is output from the DAC 10a. Therefore, a DC offset in the initial state that corresponds to a time t20 of the line 72 in FIG. 17 occurs at the baseband output terminals 28, 29. The adjustment is performed to reduce this value. Subsequently, in the step S3, the comparator 8 detects the initial DC offset. In the step S4, MSB of the DAC 10a is set to 1 by the SAR 9, and the DAC 10a outputs a compensation current in accordance with 10000. Thus, a DC offset corresponding to a time t21 of the line 72 in FIG. 17 occurs.
Next, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t20 with the DC offset at the time t21. As shown in FIG. 17, both the output values at t20 and t21 are negative and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 11000. The DAC 10a outputs a compensation current in accordance with 11000, and a DC offset corresponding to a time t22 of the line 72 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t20 with the DC offset at the time t22. As shown in FIG. 17, the output values at t20 and t22 are inverted. Therefore, in the step S7, the present bit is returned to zero, and 10000 is read from the SAR 9. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 10100. The DAC 10a outputs a compensation current in accordance with 10100, and a DC offset corresponding to a time t23 of the line 72 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t20 with the DC offset at the time t23. As shown in FIG. 17, both the output values at t20 and t23 are negative and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 10110. The DAC 10a outputs a compensation current in accordance with 10110, and a DC offset corresponding to a time t24 of the line 72 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t20 with the DC offset at the time t24. As shown in FIG. 17, both the output values at t20 and t24 are negative and thus not inverted. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is NO, the SAR 9 sets the next bit to 1 in the step S9, and the DAC 10a is set at 10111. The DAC 10a outputs a compensation current in accordance with 10111, and a DC offset corresponding to a time t25 of the line 72 in FIG. 17 occurs.
Again, in the step S5, the comparator 8 detects the present DC offset. In the step S6, the SAR 9 compares the initial DC offset with the present DC offset, i.e., the DC offset at the time t20 with the DC offset at the time t25. As shown in FIG. 17, the output values at t20 and t25 are inverted. Therefore, in the step S7, the present bit is returned to zero, and 10110 is read from the SAR 9. Then, in the step S8, the SAR 9 determines whether the bit is LSB or not. Since the result is YES, 10110 is stored in the DAC 10a. In the step S10, the operation is END, and the DC offset compensation is finished.
The above operation for adjusting the DC offset as represented by the line 72 in FIG. 17 can be summarized in FIG. 19. The initial DC offset at t20 is approximated successively during the time from t21 to t25 and compensated in the direction of decreasing the DC offset. At t26, the DC offset compensation is finished with the storage of 10110 in the DAC 10a, and the static DC offset that is output in the negative direction at the baseband output terminals 28, 29 can be compensated.
However, when the RF input signal in FIG. 10 is input to the mixer, the actual output of the mixer includes, as shown in FIG. 21, a desired signal 63 converted by the mixer, an interfering signal 64 resulting from the conversion of a high-level interfering signal by the mixer, a dynamic DC offset 65, a static DC offset 67, and a 2×fLO signal 68 converted by the mixer due to self-mixing. Therefore, if the configuration in FIG. 14 is used, the dynamic DC offset 65 has to be compensated in the following manner. First, the magnitude of the static DC offset 67 is stored, and then the magnitude of the dynamic DC offset 65 is detected as the amount by which the DC offset is changed from the static DC offset 67. Therefore, this configuration requires a means for temporally storing the magnitude of the static DC offset 67. Moreover, a radio receiver employing a direct conversion system also should have a means for compensating for the static DC offset, so that the system becomes larger and more complicated.